The present invention relates to a technology which is effective when applied to a self-alignment technique in a semiconductor device (or semiconductor integrated circuit device) such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a manufacturing method thereof.
Japanese Unexamined Patent Publication No 2008-108869 (Patent Document 1) discloses a technique in which, with regard to a manufacturing method of a SiC-semiconductor-based vertical N-channel MOSFET or MISFET, the width of a resist mask is self-alignedly increased by a heat treatment to form source regions and channel regions (P base regions) by self alignment. The publication also discloses a technique in which, after a heat treatment for the source regions and the channel regions, a gate structure is formed.
Japanese Unexamined Patent Publication No. 2008-147576 (Patent Document 2) or US Patent Publication No. 2010-35420 (Patent Document 3) corresponding thereto discloses a technique in which, with regard to a manufacturing method of a SiC-semiconductor-based vertical N-channel MOSFET or MISFET, the width of a tungsten hard mask is reduced to form source regions and channel regions by self alignment. The publication also discloses a technique in which, after a heat treatment for the source regions and the channel regions, a gate structure is formed.